Timetable and learning outcomes

Monday June 19th	Tuesday June 20th	Wednesday June 21st		Thursday June 22nd	Friday June 23rd
11.30 – 12.30 Registration	09.00 – 10.00 Circuit design - introduction to GTS software Gerhard Rzepa, Christian Schleich Conference room - B0.01	09.00 – 11.30 Lecture 2 Enhanced technologies for communication Didier Belot,  François Rivet,  Maxandre Fellman JP Dom amphiteatre - A0.85		09.00 – 12.30 Hands-on session Design and training of a basic neural network (GrAI) Part 1 Sylvain Saïghi, Adrien F. Vincent, Valentin Meunier JJ. Riviere - A0.48	10.00 – 12.00 Group 1 FVLLMONTI: system exploration with gem5-X Giovanni Ansaloni, Alireza Amirshahi, Rafael Medina Morillas Carac Nanocom	10.00 – 12.00 Group 2 Hermes: communication boosted by artificial intelligence François Rivet, Maxandre Fellman JJ. Riviere - A0.48
	10.00 – 12.00 Hands-on project Gerhard Rzepa, Christian Schleich JJ. Riviere - A0.48	11.30 - 12.30 Group 1 On-wafer measurement of emerging technology Chhandak Mukerjee JP Dom amphiteatre - A0.85	11.30 - 12.30 Group 2 Hands-on project Magalie de Matos, Marina Deng JP Dom amphiteatre - A0.85
12.30 – 13.30 Lunch	12.30 – 13.30 Lunch	12.30 – 13.30 Lunch		12.30 – 13.30 Lunch	12.00 – 13.00 Farewell lunch
13.30 - 14.00 Opening Cristell Maneux, François Rivet, Sylvain Saïghi JP Dom amphiteatre - A0.85		13.30 - 14.30 Group 1 Hands-on project Magalie de Matos, Marina Deng Carac Nanocom	13.30 - 14.30 Group 2 On-wafer measurement of emerging technology Chhandak Mukerjee Carac Nanocom	13.30 – 15.00 Hands-on session Design and training of a basic neural network (GrAI) Part 2 Sylvain Saïghi, Adrien F. Vincent, Valentin Meunier JJ. Riviere - A0.48
14.00 – 17.00 Lecture 1 Theoretical introduction to the technologies Emilio Calvanese, Sylvain Pelloquin, Thomas Mikolajick, Alice Mizrahi JP Dom amphiteatre - A0.85	13.30 – 14.30 Circuit design - introduction to CADENCE François Rivet, Nathalie Deltimple Conference room - B0.01	14.30 – 17.00 Lecture - Hardware view of neural networks and their typology Sylvain Saïghi, Adrien F. Vincent, Valentin Meunier JJ. Riviere - A0.48		15.00 – 17.00 Lecture 3 Applications Jean-Luc Rouas, Michel Paindavoine JP Dom amphiteatre - A0.85
17.00 – 18.00 Discussion JP Dom amphiteatre - A0.85	014.30 – 17.00 Hands-on project François Rivet, Nathalie Deltimple JJ. Riviere - A0.48			17.00 – 18.00 Discussion IMS laboratory hall
19.00 – 21.00 Welcome reception				19.00 – 21.00 Gala dinner

Module descriptions

Lecture 1 - Theoretical introduction to the technologies

The objective of this lecture is to present various state of the art technologies for Embedded Artificial Intelligence.

Part 1: The first part of the lecture will introduce vertical nanowire field-effect transistors (VNWFETs), a promising candidate for building blocks that enable 3D neuromorphic computing, increasing device performance and density. These innovative transistors can be configured as 3D stacked hardware layers that closely mirror the architecture of a typical neural network.

Part 2: This talk will first present a very short overview of the major analog and RF technology features of the 28nm FDSOI planar CMOS technology. The benefits of FD-SOI technology for analog/RF circuits will then be discussed, with a focus on IoT applications. Attendees will learn about design techniques that take full advantage of the unique capabilities of FD-SOI, including body biasing to efficiently modulate on the fly SoC solutions from high performance operation to energy efficiency mode. This further enhances the excellent analog/RF performances of these devices. The second part of this presentation will focus on novel design techniques that take full benefit of the new fourth transistor electrode (the body tie) and permit to get concurrent solutions that overcome the existing state of the art.

Part 3: This short lecture will provide an overview of how one can use the physics of spintronic nanodevices to implement various functions commonly found in neural networks, e.g., activation function, synaptic weight, multiply-and-accumulate (MAC) operation, etc. Exploiting the richness of intrinsic behaviours offered by such a technology could pave the way for low-latency and low-energy hardware implementations of neural networks, in particular for RF signal processing.

Part 4: Yumain, formerly Global Sensing Technologies, is one of the French leaders in embedded artificial intelligence including sensors and neural networks (edge-computing). This presentation will provide an overview of the industrial applications that require embedded artificial intelligence.

Hands-on session - Circuit design with CADENCE

Cadence is a leading EDA and Intelligent System Design provider delivering hardware, software, and IP for electronic design. Students will learn the basis of integrated circuit design using AMS 0.35um technology with the simulation of an inverter. They will play on transistor dimensions, observe the electrical characteristics by several kind of simulations and draw conclusions.

Hands-on session - Circuit design with GTS

The GTS framework provides a sophisticated graphical user interface that allows users to design 3D nano structures. Participants will learn how to view and analyse simulation results.

Lecture - On-wafer measurement of emerging technology

This tutorial will cover dedicated DC and RF measurement techniques for on-wafer characterization of emerging technologies such as vertical nanowire transistors. Particular focus will be given to novel parameter extraction methods for important device parameters such as threshold voltage, thermal impedance, traps, gate capacitances and test-structure parasitic elements. The lecture will cover the theoretical premise for several of these methods while the practical session will offer hands-on experience with some of these techniques in an experimental environment.

Hands-on session - On-wafer measurement of emerging technology

In this session, participants will be able to visit the IMS characterisation room and learn more about on-wafer measurements directly in the lab.

Lecture - Hardware view of neural networks and their typology

This talk will introduce the event-based computing paradigm for neural networks. This computational approach requires few operations and is inherently suitable for embedded artificial intelligence. After presenting the interest of low power in artificial intelligence, the presentation will review existing industrial products, which will show the interest to pursue a research effort in the field of neuromorphics. The presentation will deal with both inference and learning, based on concrete cases from research work carried out at the IMS.

Hands-on session - Design and training of a basic neural network

In this session, we will use a user-friendly simulator of spiking neural networks. This simulator will allow students to play with the different parameters of the network for a training on a standard database. The neural networks constituted should be consistent with the technological elements discussed in the previous days.

Lecture - Applications

This lecture highlights three separate applications of Embedded Artificial Intelligence including speech recognition and machine translation, 6G communications, as well as image recognition in industrial context (e.g. RF fingerprints and breast cancer). The goal of the first application is to build a lightweight in-ear device that allows on-device speech-to-speech translation, without requiring internet connectivity. The second application is motivated by the fact that Radio Frequency Integrated Circuits (RFIC) have made it possible to democratise communications with ever-greater data exchanges, allowing an increase in communication potential from one generation with 6G in sight and beyond.

Hands-on session – FVLLMONTI Demonstrator - System exploration with gem5-X

During this session, students will be introduced to the gem5-X system simulator and its main features. A hands-on tutorial will allow attendees to acquire experience in simulating the execution of AI applications on complex systems, identify bottlenecks and deploy hardware and software optimization strategies.

Hands-on session - Hermes Demonstrator - Linearization of radio frequency power amplifiers

A novel concept for linearization of Radio Frequency (RF) Power Amplifiers (PAs) will be presented. The Walsh Transform is used for both a conversion scheme from digital to analogue and as a computational basis for evaluating a digital PA predistorter (DPD) model. The mathematical properties of the Walsh theory are exploited to enhance the convergence speed of conventional DPD algorithms and reduce their computational complexity. An experimental demonstration exhibits the performances of a broadband PA’s DPD with simulations and measurements results of a 3-4GHz PA. For similar accuracy, the proposed method converges as fast as conventional algorithms with linear computational complexity instead of quadratic one.

A certificate of participation was awarded to students upon completion of the course.